The present invention relates to a method for manufacturing a capacitor of a semiconductor memory device, and more particularly to a method for manufacturing a capacitor of a highly integrated semiconductor memory having a double-cylindrical storage electrode for high reliability and large cell capacitance for memory cells.
The decrease in cell capacitance caused by reduced memory cell area is a serious obstacle to increasing packing density in dynamic random access memories (DRAMs). Thus, the problem of decreased cell capacitance must be solved to achieve higher packing density in a semiconductor memory device, since decreased cell capacitance degrades read-out capability and increases the soft error rate of a memory cell as well as consumes excessive power during low-voltage operation by impeding device operation.
Generally, in a 64 Mb DRAM having a 1.5 .mu.m.sup.2 memory cell area employing an ordinary two-dimensional stacked capacitor cell, sufficient cell capacitance cannot be obtained even though a higher dielectric constant material, e.g., tantalum oxide (Ta.sub.2 O.sub.5), is used. Therefore, stacked capacitors having a three-dimensional structure have been suggested to improve cell capacitance. Such stacked capacitors include, for example, double-stacked, fin-structured, cylindrical, spread-stacked and box-structured capacitors.
Since both outer and inner surfaces can be utilized as an effective capacitor area, the cylindrical structure is favorably suitable to the three-dimensional stacked capacitor, and is more particularly suitable for an integrated memory cell which is 64 Mb or higher. Also, an improved stacked capacitor has recently been presented, wherein pillars or another inner cylinder is formed in the interior of the cylinder. Not only may both inner and outer surfaces of the cylinder be utilized as the effective capacitor area, but also the outer surface of the pillars or the inner cylinder formed in the interior of the cylinder.
For example, T. Kaga et al. have suggested a crown-shaped stacked capacitor (see "Crown-Shaped Stacked-Capacitor Cell for 1.5 V Operation 64-Mb DRAM's" by T. Kaga et al., IEEE Transactions on Electron Devices Vol. 38 No. 2, February 1991, pp 255-260), wherein an inner cylinder is formed in the interior of the cylinder (outer cylinder); which is hereinafter referred to as a double-cylindrical capacitor.
FIGS. 1 to 4 are sectional views for illustrating a conventional manufacturing method of the double-cylindrical stacked capacitor of a semiconductor memory device, as described in the above T. Kaga et al. paper.
FIG. 1 illustrates a step of forming a first polycrystalline silicon layer 34 for forming an outer cylinder, and a spacer 36. Particularly, transistors which commonly share a bit-line 20 and a drain region 16, and which comprises a source region 14 and a gate electrode 18, respectively, are formed on an active region of a semiconductor substrate which is divided into active and isolation regions by a field oxide layer 12. An insulating layer 19 is then formed on the whole surface of the resultant structure to insulate the transistors from other conductive layers (which will be formed in the subsequent step). Thereafter, a planarization layer 22 is formed on the over insulating layer. A contact hole is then formed for connecting a storage electrode with source region 14 by partially removing planarization layer 22 and insulating layer 19 formed on source region 14. Then, a pillar electrode 30 filling the contact hole is formed by sequentially depositing a first polycrystalline silicon and first silicon dioxide layer 24, followed by a silicon nitride layer 26 and second silicon dioxide layer 32 on the surface of the insulating layer 19. Thereafter, a well is formed by partially removing second silicon dioxide layer 32, silicon nitride layer 26 and first silicon dioxide layer 24 formed over source region 14. The well is formed so that it defines individual cell units and exposes the surface of pillar electrode 30. Then, first polycrystalline silicon layer 34 for forming the outer cylinder is formed on the whole surface of the resultant structure. Then, a third silicon dioxide layer is formed on first polycrystalline silicon layer 34. The third silicon dioxide layer is anisotropically etched, thereby forming a spacer 36 on the inner sidewall of the well.
FIG. 2 illustrates a step of forming a second polycrystalline silicon layer 38 and a fourth silicon dioxide layer 40. After the steps illustrated in FIG. 1, a second polycrystalline silicon layer 38 for forming an outer cylinder is formed by depositing a third polycrystalline silicon layer on the whole surface of the resultant structure on which spacer 36 has been formed. A fourth silicon dioxide layer 40 is then formed on the whole surface of the resultant so as not to expose second polycrystalline silicon layer 38.
FIG. 3 illustrates a steps of forming a storage electrode 100. After the step of FIG. 2, fourth silicon dioxide layer 40 is etched back. The etch-back is performed on the whole surface of the resultant until a portion of second polycrystalline silicon layer 38 is exposed. Here, reference numeral 40' denotes an oxide residue formed in inner cylinder which has resulted from the etching back of fourth silicon dioxide layer 40. Then, the exposed part of second polycrystalline silicon layer 38 is anisotropically etched to thereby expose a portion of first polycrystalline silicon layer 34, which is also removed by anisotropically etching, thereby forming a storage electrode 100 comprised of outer cylinder 34' and inner cylinder 38'.
FIG. 4 illustrates a step of completing a capacitor After removing oxide residue 40', spacer 36 and second silicon dioxide layer 32, a dielectric layer 110 is formed on the whole surface of storage electrode 100. Then, a plate electrode 120 is formed by depositing a fourth polycrystalline silicon material on the whole surface of the resultant structure, thereby completing a capacitor comprised of storage electrode 100, dielectric film 110, and plate electrode 120.
According to the above conventional method for manufacturing a capacitor of a semiconductor memory device, a double cylinder-type storage electrode having an inner cylinder inside an outer cylinder can be manufactured, thereby enlarging the cell capacitance of a semiconductor memory device. However, this method has certain drawbacks.
First, as shown in FIG. 1, after the contact hole for the formation of the pillar electrode is formed, the hole is covered with the first polycrystalline silicon layer 34. The precise covering of the contact hole with the first polycrystalline silicon layer 34 is crucial because the shape of the outer cylinder formed over the contact hole depends on the state in which the first polycrystalline silicon layer 34 covers the contact hole. This process is very difficult to satisfactorily achieve.
Second, as shown in FIG. 1, when forming the well by anisotropically etching second silicon dioxide layer 32, the well is apt to be formed so as to have a sloped sidewall, which causes voids between cells when subsequently forming the plate electrode. Thus, the electrical characteristics of the memory device are potentially deteriorated.
Thirdly, as shown in FIG. 3, etching-back fourth silicon dioxide layer 40 is difficult to control, so uniform cell capacitance cannot be easily realized.
Fourth, as shown in FIG. 2, since the storage electrode is a combination of three polycrystalline silicon layers, a native oxide layer may form on the inter-surfaces of the polycrystalline silicon layers. This leads to an increase in the series electrical resistance and a decrease in the interlayer adherence so that fragments of the polycrystalline silicon layer may be lost when force is applied thereto, for example, when spinning the wafer.
Fifth, since the conventional double-cylindrical electrode described above has sharply edged ends, (e.g., at the ends of the inner and outer cylinders) there is a high probability that a leakage current is created.